1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a static random access memory device (SRAM) which can be manufactured by a CMOS standard logic manufacturing process and a method for manufacturing the same.
2. Description of the Related Art
Static random access memories (SRAMs) are easy to use and operate faster compared to dynamic random access memories (DRAM). For these reasons, the SRAMs have been used typically as a cache memory or a system memory in terminals. Recently, a development tendency of semiconductor devices towards high performance and composite functionality has raised use of SRAM embedded logic products, in which SRAMs and logic products are merged in one chip.
Referring to FIG. 1, an equivalent circuit diagram of a unit memory cell of a general SRAM device is shown. As shown in FIG. 1, the SRAM cell is composed of two access transistors Q1 and Q2 and a flip-flop circuit including a pair of CMOS inverters. The first inverter is composed of transistors Q5 and Q3, and the second inverter is composed of transistors Q6 and Q4. SRAM cells are classified into one of three types including a resistor type SRAM, a thin film transistor type SRAM and a pull CMOS type SRAM, according to the type of load transistors, i.e., transistors Q5 and Q6, of the flip-flop. Recently, the increasing need for low power supply voltage and high-speed products has raised interest in the full CMOS type SRAM.
However, as shown in FIG. 1, the full CMOS SRAM requires six transistors Q1 through Q6 and twelve nodes C1 through C12 to constitute one memory cell. Thus, it has high cell area, resulting in the disadvantage of less integration density, compared to the other two types of cells, which require only four transistors.
In FIG. 1, the first access transistor Q1 and the second access transistor Q2 have their gates connected respectively via the nodes C9 and C10 to a word line WL, and their sources connected respectively via the nodes C7 and C8 to first and second bit lines BL1 and BL2. The first CMOS inverter, which is composed of the first load transistor Q5 and the first drive transistor Q3, has an input connected via nodes C4 and C2, respectively, to the output of the second CMOS inverter and the drain of the second access transistor Q2, and an output connected via the nodes C1 and C3, respectively, to the drain of the first access transistor Q1 and the input (i.e., the node C6) of the second CMOS inverter. The second CMOS inverter, which is composed of the second load transistor Q6 and the second drive transistor Q4, has an input (i.e., the node C6) connected via the nodes C3 and C1, respectively, to the output of the first CMOS inverter and the drain of the first access transistor Q1, and an output connected via the nodes C2 and C4, respectively, to the drain of the second access transistor Q2 and the input (i.e., the node C5) of the first CMOS inverter. Also, the drains of the first and second load transistors Q5 and Q6 are connected via the node C12 to a first power supply voltage Vcc, and the sources of the first and second drive transistors Q3 and Q4 are connected via the node C11 to a second power supply voltage Vss.
FIG. 2 is a sectional view showing part of the conventional full CMOS type SRAM cell of FIG. 1, in which the input of the first CMOS inverter (the node C5 formed on the gate of the first load transistor Q5), the source 16 of the second load transistor Q6 and the drain 18 of the second access transistor Q2 (which shares the drain 18 with the second drive transistor Q4) are connected via the nodes C4 and C2 by a local interconnection line 22.
In FIG. 2, reference numeral 10 represents a semiconductor substrate, reference numeral 12 represents a field oxide layer, reference numeral 14 represents the gate of the first load transistor Q5, reference numeral 16 represents the source of the second load transistor Q6, reference numeral 18 represents the drain of the second access transistor Q2 and the second drive transistor Q4, reference numeral 20 represents an insulating layer, reference numeral 22 represents the local interconnection line, reference numeral 24 represents a first interlayer dielectric (ILD) film, reference numeral 26 represents a word line, reference numeral 28 represents a second ILD film, reference numeral 30 represents a power supply line, reference numeral 32 represents a third ILD film, and reference numeral 34 represents a bit line.
The input (refer to the gate 14 of the first load transistor Q5) of the first CMOS inverter is connected via the first local interconnection line, which is formed of a bilayer including a titanium (Ti) layer and a titanium nitride (TiN) layer, to the source 16 of the second load transistor Q6 and the drain 18 of the second access transistor Q2 and the second drive transistor Q4. The input (not shown) of the second CMOS inverter is connected via a second local interconnection line (not shown) to the source (not shown) of the first load transistor Q5 and the drain (not shown) of the first access transistor Q1 and the first drive transistor Q3.
The word line 26 is connected to the gates of the first and second access transistors Q1 (not shown) and Q2. The power supply line 30 and the bit lines are formed in different layers with a metal interconnection. In FIG. 2, the power supply line 30 extends in the lateral direction and the bit line 34 extends in the vertical direction.
Merging the SRAM cell of FIG. 2 with a logic device requires additional processes based on a general CMOS standard logic manufacturing process, thereby increasing the manufacturing cost due to the need for additional photolithography processes and making the overall process complicated. In particular, as shown in FIG. 2, for the connection between the input of the first CMOS inverter and the output of the second CMOS inverter, and between the output of the second CMOS inverter and the input of the first CMOS inverter, the conventional full CMOS type SRAM requires the formation of the local interconnection line having a bilayer structure including, for example, a Ti layer and a TiN layer, in addition to the general CMOS standard logic manufacturing process, and in turn additional masks therefor.
The word line 26 is formed of polyslicon, which is also used in forming the gate of the load transistor Q5. However, similar to the formation of the local interconnection line, additional processes in addition to the general CMOS standard logic manufacturing process must be carried out for the word line 26. Two more masks, one for the word line and the other for the contact hole connecting the word line and a transistor, are required, rendering the manufacturing process complicated.
Also, when the SRAM cell of FIG. 2 is merged with a logic device without performing additional processes, the size of the SRAM cell increases beyond a desired size.
To solve the above problems, it is an object of the present invention to provide a static random access memory (SRAM) device which can be manufactured by standard CMOS logic manufacturing processes without the need for additional masks or processes, wherein an increase in cell size is minimized.
Another object of the present invention is to provide a method for manufacturing an SRAM device by standard CMOS logic manufacturing processes without the need for additional masks or processes, wherein an increase in cell size is minimized.
The first object is achieved by a SRAM device comprising: first and second access transistors each having a gate connected to a word line and a source connected to a bit line. The SRAM also includes a first inverter including a first drive transistor and a first load transistor and a second inverter including a second drive transistor and a second load transistor. A first connection line connects the input of the first inverter, the output of the second inverter and the drain of the second access transistor. A second connection line connects the input of the second inverter, the output of the first inverter and the drain of the first access transistor. In the device of the invention, all conductive layers, other than the gates of the two access transistors and the gates of the transistors for the first and second inverters, are formed of metal in different layers.
In one embodiment, the multiple metal layers include a first metal layer which forms the first and second connection lines, a second metal layer which forms the word line, and a third metal layer which forms bit lines and power supply lines connected to the first and second inverters.
In one embodiment, the multiple metal layers include a first metal layer which forms the first and second connection lines, a second metal layer which forms the word line, a third metal layer which forms bit lines, and a fourth metal layer which forms power supply lines connected to the first and second inverters.
In another aspect, the SRAM device according to the present invention includes a flip-flop circuit including two access transistors and a pair of inverters. The SRAM device comprises a semiconductor substrate in which parallel first and second active regions of a first conductive type are arranged and third and fourth active regions of a second conductive type are arranged between the first and second active regions. First conductive layers act as the gates of the first access transistor and the first drive transistor which extend perpendicular to the first active region for serial connection between the first access and drive transistors, as the gates of the second access transistor and the second drive transistors which extend perpendicular to the second active region for serial connection between the second access and drive transistors, as the gate of the first load transistor which extends perpendicular to the third active region, and as the gate of the second load transistor which extends perpendicular to the fourth active region. Second conductive layers act as a first connection line which connects the drain of the first access transistor and the first drive transistor, the gate of the second drive transistor, the gate of the second load transistor connected to the gate of the second drive transistor, and the source of the first load transistor, and as a second connection line which connects the drain of the second access transistor and the second drive transistor, the gate of the first drive transistor, the gate of the first load transistor connected to the gate of the first drive transistor, and the source of the second load transistor. A third conductive layer acts as a word line connected to the gate of the first access transistor and the gate of the second access transistor. Fourth conductive layers act as a first power supply line connected to the drain of the first load transistor and the drain of the second load transistor, as a second power supply line connected to the source of the first drive transistor and the source of the second drive transistor, as a first bit line connected to the source of the first access transistor, and as a second bit line connected to the source of the second access transistor.
In one embodiment of this aspect of the invention, the first and second active regions are formed across a cell in a bar shape, and the third and fourth active regions are arranged in a staggered manner parallel to the first and second active regions. The first active region can have a wider width at regions overlapped by the gate of the first drive transistor than at regions overlapped by the gate of the first access transistor, and the second active region can have a wider width at regions overlapped by the gate of the second drive transistor than at regions overlapped by the gate of the second access transistor.
In addition, in one embodiment of this aspect of the invention, the gate of the first drive transistor arranged perpendicular to the first active region and the gate of the first load transistor arranged perpendicular to the third active region are laterally connected to cover one end of the fourth active region, and the gate of the second drive transistor arranged perpendicular to the second active region and the gate of the second load transistor arranged perpendicular to the fourth active region are laterally connected to cover one end of the third active region.
The gate of the first access transistor, the gate of the second drive transistor and the gate of the second load transistor can be located in a line, and the gate of the second access transistor, the gate of the first drive transistor and the gate of the first load transistor can be located in another line parallel to the gates of the first access transistor, second drive transistor and second load transistor.
The first connection line and the second connection line can be arranged, not overlapping each other, and the elements connected to the second connection line are not overlapped by the first connection line, and the elements connected to the first connection line are not overlapped by the second connection line.
The first connection line can connect the drain of the first access transistor and the first drive transistor, the gate of the second drive transistor, the gate of the second load transistor, and the source of the first load transistor via a contact hole C1/C3 formed on the drain of the first access transistor and the first drive transistor and a contact hole C6 formed over the gate of the second load transistor overlapped by the one end of the third active region, and the source of the first load transistor, and the second connection line can connect the drain of the second access transistor and the second drive transistor, the gate of the first drive transistor, the gate of the first load transistor and the source of the second load transistor via a contact hole C2/C4 formed on the drain of the second access transistor and the second drive transistor and a contact hole C5 formed over the gate of the first load transistor overlapped by one end of the fourth active region, and the source of the second load transistor. The first and second connection lines can be formed of polysilicon, amorphous silicon, aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co) or copper (Cu).
The word line can be connected to a first pad layer C9 which is formed of the first conductive layer and is connected to the gate of the first access transistor, and a first pad layer C10 which is formed of the first conductive layer and is connected to the gate of the second access transistor. The word line may be arranged parallel to the gates of the transistors and across a cell in a bar shape.
In one embodiment, the first power line, the second power line, the first bit line and the second bit line are arranged perpendicular to the word line. The first power supply line can be arranged between and parallel to the first and second bit lines, and the second power supply lines can be arranged between and parallel to the first and second bit lines between which the first power supply line is not formed.
The first power supply line can supply the supplying power supply voltage to the drains of the first and second load transistors, respectively, via a first pad layer C12 formed of the second conductive layer over the drain of the first load transistor and via a second pad layer C12 formed of the third conductive layer over the drain of the second load transistor. The second power supply line can supply ground voltage to the sources of the first and second drive transistors, respectively, via a first pad layer C11 formed of the second conductive layer over the source of the first drive transistor and via a second pad layer C11 formed of the third conductive layer over the source of the second drive transistor. The first bit line can supply a bit line or bit line bar voltage to the source of the first access transistor via a first pad layer C7 formed of the second conductive layer and a first pad layer C7 formed of the third conductive layer over the source of the first access transistor. The second bit line can supply a bit line bar or bit line voltage to the source of the second access transistor via a first pad layer C8 formed of the second conductive layer and a second pad layer C8 formed of the third conductive layer over the source of the second access transistor.
In one embodiment, the second through fourth conductive layers are a metal layer.
In another aspect of the invention, there is provided an SRAM including a flip-flop circuit including two access transistors and a pair of inverters. The device includes a semiconductor substrate in which parallel first and second active regions of a first conductive type are arranged and third and fourth active regions of a second conductive type are arranged between the first and second active regions. First conductive layers act as (i) the gates of the first access transistor and the first drive transistor which extend perpendicular to the first active region for serial connection between the first access and drive transistors, (ii) the gates of the second access transistor and the second drive transistors which extend perpendicular to the second active region for serial connection between the second access and drive transistors, (iii) the gate of the first load transistor which extends perpendicular to the third active region, and (iv) the gate of the second load transistor which extends perpendicular to the fourth active region. Second conductive layers formed of a metal layer act as a first connection line which connects the drain of the first access transistor and the first drive transistor, the gate of the second drive transistor, the gate of the second load transistor connected to the gate of the second drive transistor, and the source of the first load transistor, and as a second connection line which connects the drain of the second access transistor and the second drive transistor, the gate of the first drive transistor, the gate of the first load transistor connected to the gate of the first drive transistor, and the source of the second load transistor. A third conductive layer formed of a metal layer acts as a word line connected to the gate of the first access transistor and the gate of the second access transistor. Fourth conductive layers formed of a metal layer act as a first bit line connected to the source of the first access transistor and as a second bit line connected to the source of the second access transistor. Fifth conductive layers formed of a metal layer act as a first power supply line connected to the drain of the first and second load transistors, and as a second power supply line connected to the source of the first and second drive transistors.
The second object is achieved by a method for manufacturing a static random access memory (SRAM) device including a flip-flop including two access transistors and a pair of inverters. In accordance with the method, first and second active regions are defined in a semiconductor substrate parallel to each other, and third and fourth active regions are simultaneously arranged between the first and second active regions parallel to each other. A gate oxide layer is formed on the substrate having the first through fourth active regions, and the gates of the first access transistor and the first drive transistor are formed perpendicular to the first active region for serial connection between the first access transistor and the first drive transistor. The gates of the second access transistor and the second drive transistor are formed perpendicular to the second active region for serial connection between the second access transistor and the second drive transistor. The gate of the first load transistor is formed perpendicular to the third active region, and the gate of the second load transistor is formed perpendicular to the fourth active region. Then, a first interlayer dielectric (ILD) film is formed on the substrate having the gates of the transistors, and the first ILD film is selectively etched to form (i) a contact hole C1/C3 over the drain of the first access transistor and the first drive transistor, (ii) a contact hole C6 over the gate of the second load transistor and the source of the first load transistor connected to the gate of the second drive transistor, (iii) a contact hole C2/C4 over the drain of the second access transistor and the first drive transistor, and (iv) a contact hole C5 over the gate of the first load transistor and the source of the second load transistor connected to the gate of the first drive transistor. A second conductive layer is formed and selectively patterned to form a first connection line for connecting the drains of the first access transistor and first drive transistor, the gates of the second drive transistor and second load transistor, and the source of the first load transistor via the contact holes C1/C3 and C6 and to form a second connection line for connecting the drains of the second access transistor and second drive transistor, the gates of the first drive transistor and first load transistor, and the source of the second load transistor via the contact holes C2/C4 and C5. Then, a second ILD film is formed and then selectively patterned to form a first via hole C9 over the gate of the first access transistor and a first via hole C10 over the gate of the second access transistor. A third conductive layer is formed and then selectively patterned to form a word line connected to the gates of the first access transistor and the second access transistor via the first via holes C9 and C10, respectively. A second ILD film is formed and selectively patterned to form a second via hole C12 over the drain of the first and second load transistors, a second via hole C11 over the source of the first and second drive transistors, a second via hole C7 over the source of the first access transistor, and a second via hole C8 over the source of the second access transistor. Then, a fourth conductive layer is formed and selectively patterned to form a first power supply line connected to the drain of the first and second load transistors via the second via hole C12, a second power supply line connected to the source of the first and second drive transistors via the second via hole C11, a first bit line connected to the source of the first access transistor via the second via hole C7, and a second bit line connected to the source of the second access transistor via the second via hole C8.
In one embodiment of this aspect, the first and second active regions are formed across a cell in a bar shape. The third and fourth active regions can be arranged in a staggered manner parallel to the first and second active regions.
In one embodiment, the first active region has a wider width at regions overlapped by the gate of the first drive transistor than at regions overlapped by the gate of the first access transistor. The second active region has a wider width at regions overlapped by the gate of the second drive transistor than at regions overlapped by the gate of the second access transistor.
In one embodiment, in forming the contact holes in the first ILD film along with the contact holes C/C3, C2/C4, C5 and C6, contact holes C7 and C9 are respectively formed over the source and gate of the first access transistor, contact holes C11 are formed over the sources of the first and second drive transistors, contact holes C8 and C10 are respectively formed over the source and gate of the second access transistor, and contact holes C12 are formed over the drains of the first and second load transistors.
In one embodiment, before forming the second conductive layer, tungsten is deposited to fill the contact holes C1/C2, C2/C4, C5 and C6. The tungsten layer is planarized until the surface of the first ILD film is exposed, to form a first plug C1/C3 filling the contact hole C1/C3, a first plug C2/C4 filling the contact hole C2/C4, a first plug C5 filling the contact hole C5, and a first plug C6 filling the contact plug C6. Here, along with the first plugs C1/C3, C2/C4, C5 and C6, first plugs C7 and C9 can be respectively formed in the contact holes C7 and C9 formed respectively over the source and gate of the first access transistor, first plugs C11 can be formed in the contact holes C11 formed respectively over the sources of the first and second drive transistors, first plugs C8 and C10 can be respectively formed in the contact holes C8 and C10 formed respectively over the source and gate of the second access transistor; and first plugs C12 can be formed in the contact holes C12 formed over the drains of the first and second load transistors.
In one embodiment, in patterning the second conductive layer along with the first and second connection lines a first pad layer C7 connected to the first plug C7, a first pad layer C9 connected to the first plug C9, a first pad layer C11 connected to the first plug 11, a first pad layer C8 connected to the first plug C8, a first pad layer C10 connected to the first plug C10, and a first pad layer C12 connected to the first plug C12 are formed. The second conductive layer can be formed of polysilicon, amorphous silicon, aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co) or copper (Cu), and the third and fourth conductive layers can be formed of Al or Cu.
The contact holes, the first via holes and the second via holes can be filled with tungsten to form first plugs, second plugs and third plugs, respectively.
In defining the active regions, each step for forming fourth conductive layers can be accompanied with general CMOS manufacturing process.